Project overview
Deli Counter is a project we were assigned to create a counter that would count to 80 and stop at 80. It would have two circuits that are connected by one reset button and a logic gate. The first counter would count to 9 and then shift the next counter +1, and when the 2nd counter reaches 8 then the first counter stops at 0. And then you would start again by pressing the reset button.
multisim circuit
Mrs. Zienty did not sign anything but knows that it works.
pld circuit
Mrs. Zienty did not sign anything but knows that it works.
bill of materials
Material |
Quantity |
Wires |
A Lot |
DIG0 |
1 |
DIG1 |
1 |
S0 switch |
1 |
final project conclusions
SSI vs MSI circuits:
SSI means small scale integration that is made up of logic gates. SSI has between 3 to 30 gates/chips. MSI means medium scale integration that is made with logic gates. MSI has between 30 to 300 gates/chips.
Limitations of MSI Counter (74LS93):
The flip-flops are not pre-settable so the count must always start at zero, as well as the 74LS93 only counts up.
Meaning of "ripple effect":
The ripple effect is defined as "the fluctuating AC component in the rectified DC output" which means that there is a delay when the clock shifts and the binary numbers on the asynchronous counter changes and the number displayed changes. There is a delay when the number changes on an asynchronous counter.
Set Up:
When I press a switch, the whole circuit resets back to 0 and resets count. After that, when the first counter counts up to 9 and starts back at 0, the next circuit shifts +1 caused by the first circuit. Which is connected by a logic gate that is responsible for shifting the second circuit as a result of the first circuit triggering a shift. When the signal travels to the clock input of JK unit, it starts the count up for each shift in binary. With PLD, I looked at the pins and connected the same number assigned on the integrated circuit and connected that to the switch, DIG0, and DIG1. As each input like the switch would cause a reset, or like the DIG0 and DIG1 which have outputs for each segment that would allow for us to see the output.
SSI means small scale integration that is made up of logic gates. SSI has between 3 to 30 gates/chips. MSI means medium scale integration that is made with logic gates. MSI has between 30 to 300 gates/chips.
Limitations of MSI Counter (74LS93):
The flip-flops are not pre-settable so the count must always start at zero, as well as the 74LS93 only counts up.
Meaning of "ripple effect":
The ripple effect is defined as "the fluctuating AC component in the rectified DC output" which means that there is a delay when the clock shifts and the binary numbers on the asynchronous counter changes and the number displayed changes. There is a delay when the number changes on an asynchronous counter.
Set Up:
When I press a switch, the whole circuit resets back to 0 and resets count. After that, when the first counter counts up to 9 and starts back at 0, the next circuit shifts +1 caused by the first circuit. Which is connected by a logic gate that is responsible for shifting the second circuit as a result of the first circuit triggering a shift. When the signal travels to the clock input of JK unit, it starts the count up for each shift in binary. With PLD, I looked at the pins and connected the same number assigned on the integrated circuit and connected that to the switch, DIG0, and DIG1. As each input like the switch would cause a reset, or like the DIG0 and DIG1 which have outputs for each segment that would allow for us to see the output.